1. Field of the Invention
The present invention relates in general to an electrostatic discharge (ESD) protection component, and more particularly to an ESD protection component using dummy gate structures to isolate substrate-triggering regions.
2. Description of the Related Art
As manufacturing processes progress, highly integrated designs such as miniaturized components, shallower junction depths, thinner gate oxide layers, lightly-doped drain (LDD) structures and salicide process have made integrated circuits (ICs) more vulnerable to ESD damage. ESD protection circuits or ESD protection components are frequently built into chips to prevent such damage.
N-type metal-oxide-semiconductors (NMOSs) with finger-type structure are usually used as ESD protection components to release transient current during an ESD event. However, ESD robustness may not be improved as the size of the NMOSs become larger, due to lack of turn-on uniformity.
The turn-on uniformity of the finger-type NMOSs can be enhanced with gate-driven or substrate-triggered techniques as shown in FIGS. 1a and 1b. With a gate-driven technique, gate-oxide layers at gates of MOSs are easily damaged when the gates are overstressed and large ESD current flows through the surface channel under the gates. ESD robustness of the gate-driven MOSs is decreased when the gate voltage is somewhat increased. With a substrate-triggered technique, on the other hand, ESD robustness increases with growing bias current at a substrate. Substrate-triggered techniques are thus more suitable for solving ESD problems in ICs.
Substrate-triggered techniques have been disclosed in U.S. Pat. Nos. 5,744,842 and 6,072,219 in FIGS. 2, 3a and 3b. In both cases, field oxide layers are used to isolate substrate triggering doped regions and doped regions used as drains/sources of a metal-oxide-semiconductor field-effect-transistor (MOSFET). Field oxide layers can be formed by local oxidation (LOCOS) or shallow trench isolation (STI).
The present invention is directed to a substrate-triggered ESD protection component having high triggering speed, and its application in a circuit.
The present is further directed to a substrate-triggered ESD protection component having smaller size, and its application in a circuit.
Accordingly, the present invention provides a substrate-triggered ESD protection component having dummy gate structures. The ESD protection component comprises a bipolar junction transistor (BJT), a substrate-triggering region to provide triggering current and a dummy gate structure. The BJT comprises a collector. The dummy gate structure has a poly-silicon gate adjacent to the collector and the substrate-triggering region. An emitter of the BJT is coupled to a power line, the collector is coupled to a pad, and the substrate-triggering region is coupled to an ESD detection circuit. During normal circuit operations, a base of the BJT is coupled with the power line through the ESD detection circuit. When an ESD event occurs between the pad and the power line, a triggering current is provided to the substrate-triggering region by the ESD detection circuit to trigger the BJT and release ESD current.
The BJT can be a lateral BJT parasitic under a gate structure of a MOSFET. The MOSFET can be a single MOSFET or a stacked MOSFET.
The present invention further provides an ESD protection circuit, comprising an ESD detection circuit, and the substrate-triggered ESD protection component having the dummy gate structures described. During normal circuit operations, the base is coupled to the power line. When an ESD event occurs between the pad and power line, the substrate-triggering current is provided by the ESD detection circuit to trigger the BJT and release ESD current.
The present invention further provides more structures implementing the substrate-triggering ESD protection component of the present invention, including finger-type MOSFET and polygon MOSFET structures.
According to an ESD protection component of the present invention, a substrate-triggering region is closer to a base of a parasitic BJT in an ESD protection component. The ESD protection component is triggered much faster during an ESD event, resulting in better ESD robustness.